1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to a programmable logic device having logic blocks capable of directly providing a constant value to an adder circuit without first passing the constant value through a look up table.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. The blocks of logic, often referred to by such names as Logic Elements (LEs), Adaptive Logic Modules (ALMs), or Complex Logic Blocks (CLBs), usually include one or more look up table (LUTs), programmable registers, adders and other circuitry to implement various logic and arithmetic functions.
One problem with current PLDs is implementing an adding function between a constant value and a non-constant value. With the logic blocks of known PLDs, the constant value is passed through a LUT before providing the constant value to the adders in the logic block. In this mode, the LUT is simply being used as a “conduit”, preventing or limiting the LUT from performing other logic functions. As a result, the efficiency of the PLD is degraded.
A higher efficiency PLD having logic blocks capable of performing addition with a constant and non-constant value where the constant value is provided directly to an adder, without first passing it through a LUT, is therefore needed.